X86
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x86 ime je obitelj mikroprocesora koji rabe određnu arhitekturu naredbenog skupa, koji je prvotno bio razvijen za mikroprocesor Intel 8086 i Intel 8088 od strane tvrtke Intel. Inače, Intel nije jedina tvrtka koja je doprinijela razvoju x86 arhitekture jer tvrtke kao AMD i VIA Technologies su u mnogome doprinijele razvoju x86 arhitekture.
Pojam x86 u 1980-im i početkom 1990ih označavao je sve mikroprocesore koji su bili kompatibilini sa 16-bitnim Intel 8086. Pojam x86 danas se rabi za mikroprocesore koji su binarno sukladni s 32-bitnim naredbenim skupom koji se prvotno pojavio s mikroprocesorom Intel 80386 1985. godine. AMD je između 1999. i 2003. godine proširio naredbenu arhitekturu x86 s 32 na 64-bita, i ova proširna arhitektura dobila je naziv x86-64 dok u kasnijim dokumentima ovo je dobilo naziv AMD64. Ovu proširenu arhitekturu je usvojila i tvrtka Intel za svoje proizvode, i u svojoj tehničkoj dokumentaciji Intel je ovo prvo referiralo pod nazivom IA32e, potom EM64T, da bi na kraju usvojili Intel 64. Microsoft i Sun Microsystems za ovu arhitekturu rabile su naziv x64, dok su pojedine Linux distributije i BSD rabile naziv AMD64. U svoj operacijskom sustavu Windows, tvrtka Microsoft rabi naziv x86 za 32-bitnu inačicu, dok za 64-bitnu rabi x64.
| Generacija | Opaska | Istaknutiji modeli | Addresni prostor | Istaknute značajke | |||
|---|---|---|---|---|---|---|---|
| Linearni | Virtualni | Fizički | |||||
| x86 | 1. | 1978. | Intel 8086, Intel 8088(1979) | 16-bitni | NA | 20-bitni | 16-bitni ISA, IBM PC (8088), IBM PC/XT (8088) |
| 1982. | Intel 80186, Intel 80188 NEC V20/V30(1983) | 8086-2 ISA, ugrađeni (80186/80188) | |||||
| 2. | Intel 80286 i kolonovi | 30-bitni | 24-bit | zaštićeni mod, IBM PC XT 286, IBM PC AT | |||
| 3. (IA-32) | 1985 | Intel 80386, AMD Am386 (1991) | 32-bit | 46-bitni | 32-bitni | 32-bitni ISA, straničenje, IBM PS/2 | |
| 4. (protočnjak, priručna memorija) | 1989 | Intel 80486 Cyrix Cx486S/DLC(1992) AMD Am486(1993.)/Am5x86(1995) | pipelining, on-die x87 FPU (486DX), on-die priručna memorija | ||||
| 5. (Superscalar) | 1993 | Intel Pentium, Pentium MMX(1996) | Superscalar, 64-bit sabirnica, brži FPU, MMX (Pentium MMX), APIC, SMP | ||||
| 1994. | NexGen Nx586 AMD 5k86/K5 (1996) | Diskretna multiarhitektura (µ-op prevođenje) | |||||
| 1995. | Cyrix Cx5x86 Cyrix 6x86/MX(1997.)/MII(1998.) | dinamično izvršavanje | |||||
| 6. (PAE, µ-op prevođenje) | 1995. | Intel Pentium Pro | 36-bitni (PAE) | µ-op prevođenje, naredba za uvjetno pomicanje, dinamički izvršavanje, spekulativno izvršavanje, trostrani superskalarni x86, superskalarni FPU, Proširena fizička adresa, ugrađena L2 priručna memorija | |||
| 1997. | Intel Pentium II, Pentium III (1999.) Celeron(1998.), Xeon(1998.) | on-package (Pentium II) or on-die (Celeron) L2 priručna memorija, SSE (Pentium III), SLOT 1, Socket 370 ili SLOT 2 (Xeon) | |||||
| 1997. | AMD K6/K6-2(1998.)/K6-III(1999.) | 32-bitni | 3DNow!, troslojna priručna memorija (K6-III) | ||||
| Enhanced Platform | 1999. | AMD Athlon, Athlon XP/MP(2001.) Duron(2000.), Sempron(2004.) | 36-bitni | MMX+, 3DNow!+, dvoprotočne sabirnice, Slot A ili Socket A | |||
| 2000. | Transmeta Crusoe | 32-bitni | CMS pogonjen s procesorom na bazi x86, VLIW-128 core, on-die memory controller, on-die PCI bridge logic | ||||
| Intel Pentium 4 | 36-bitni | SSE2, HTT (Northwood), NetBurst, quad-pumped bus, Trace Cache, Socket 478 | |||||
| 2003. | Intel Pentium M Intel Core (2006.), Pentium Dual-Core (2007) | µ-op fusion, XD bit (Dothan) (Intel Core "Yonah") | |||||
| Transmeta Efficeon | CMS 6.0.4, VLIW-256, NX bit, HT | ||||||
| IA-64 | Prijelaz na 64-bitnu arhitekturu 1999 ~ 2005 | 2001 | Intel Itanium (2001 ~ 2017) | 52-bitni | 64-bitna EPIC arhitektura, 128-bit VLIW instruction bundle, on-die hardware IA-32 H/W enabling x86 OSes & x86 applications (early generations), software IA-32 EL enabling x86 applications (Itanium 2), Itanium register files are remapped to x86 registers | ||
| x86-64 | Prošireni 64-bitni od 2001. | x86-64 is the 64-bit extended architecture of x86, its Legacy Mode preserves the entire and unaltered x86 architecture. The native architecture of x86-64 processors, residing in the 64-bit Mode, lacks of access mode in segmentation, presenting 64-bit architectural-permit linear address space, currently, only 48-bit of which is implemented; an adapted IA-32 architecture residing in the Compatibility Mode alongside 64-bit Mode is provided to support most x86 applications | |||||
| 2003 | Athlon 64/FX/X2(2005), Opteron Sempron(2004)/X2(2008) Turion 64(2005)/X2(2006) | 40-bit | AMD64 (except some Sempron processors presented as purely x86 processors), on-die memory controller, HyperTransport, on-die dual-core (X2), AMD-V (Athlon 64 Orleans), Socket 754/939/940 or AM2 | ||||
| 2004 | Pentium 4 (Prescott) Celeron D, Pentium D (2005) | 36-bit | EM64T (enabled on selected models of Pentium 4 and Celeron D), SSE3, 2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx), Intel VT(Pentium 4 6x2), socket LGA 775 | ||||
| 2006 | Intel Core 2 Pentium Dual-Core (2007) Celeron Dual-Core (2008) | Intel 64 (<<== EM64T), SSSE3(65nm), wide dynamic execution, µ-op fusion, macro-op fusion in 16-bit and 32-bit mode,[1][2] on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom") | |||||
| 2007 | AMD Phenom/II(2008) Athlon II(2009), Turion II(2009) | 48-bit | Monolithic quad-core(X4)/triple-core(X3), SSE4a, Rapid Virtualization Indexing (RVI), HyperTransport 3, AM2+ or AM3 | ||||
| 2008 | Intel Core 2 (45nm) | 40-bit | SSE4.1 | ||||
| Intel Atom | netbook or low power smart device processor, P54C core reused | ||||||
| Intel Core i7 Core i5 (2009), Core i3 (2010) | QuickPath, on-chip GMCH (Clarkdale), SSE4.2, Extended Page Tables (EPT) for virtualization, macro-op fusion in 64-bit mode,[1][2] (Intel Xeon "Bloomfield" with Nehalem microarchitecture) | ||||||
| VIA Nano | hardware-based encryption; adaptive power management | ||||||
| 2010 | AMD FX | 48-bit | octa-core, CMT(Clustered Multi-Thread), FMA, OpenCL, AM3+ | ||||
| 2011 | AMD APU A and E Series (Llano) | 40-bit | on-die GPGPU, PCI Express 2.0, Socket FM1 | ||||
| AMD APU C, E and Z Series (Bobcat) | 36-bit | low power smart device APU | |||||
| Intel Core i3, Core i5 and Core i7 (Sandy Bridge/Ivy Bridge) | Internal Ring connection, decoded µ-op cache, LGA 1155 socket. | ||||||
| 2012 | AMD APU A Series (Bulldozer, Trinity and later) | 48-bit | AVX, Bulldozer based APU, Socket FM2 or Socket FM2+ | ||||
| Intel Xeon Phi (Knights Corner) | 48-bit | coprocessor OS powered PCI-E Card Formed coprocessor for XEON based system, Many Core Chip, In-order P54C, very wide VPU (512-bit SSE), LRBni instructions (8× 64-bit) | |||||
| 2013. | AMD Jaguar (Athlon, Sempron) | 48-bit | SoC, game console and low power smart device processor | ||||
| Intel Silvermont (Atom, Celeron, Pentium) | 36-bit | SoC, low/ultra-low power smart device processor | |||||
| Intel Core i3, Core i5 and Core i7 (Haswell/Broadwell) | 39-bit | AVX2, FMA3, TSX, BMI1, and BMI2 instructions, LGA 1150 socket | |||||
| 2015 | Intel Broadwell-U (Intel Core i3, Core i5, Core i7, Core M, Pentium, Celeron) | SoC, on-chip Broadwell-U PCH-LP (Multi-chip module) | |||||
| 2015/2016 | Intel Skylake/Kaby Lake/Cannon Lake (Intel Core i3, Core i5, Core i7) | 46-bit | AVX-512 (restricted to Cannon Lake-U and workstation/server variants of Skylake) | ||||
| 2016 | Intel Xeon Phi (Knights Landing) | 48-bit | Many-core CPU and coprocessor for Xeon systems, Airmont (Atom) core based | ||||
| 2016 | AMD Bristol Ridge (AMD (Pro) A6/A8/A10/A12) | 48-bit | Integrated FCH on die, SoC, AM4 socket | ||||
| 2017 | AMD Ryzen Series/AMD Epyc Series | AMD's implementation of SMT, on-chip multiple dies. | |||||
| 2017 | Zhaoxin WuDaoKou (KX-5000, KH-20000) | Zhaoxin's first brand new x86-64 architecture | |||||
| 2018/2019 | Intel Sunny Cove (Ice Lake-U and Y) | 57-bit | Intel's first implementation of AVX-512 for the consumer segment. Addition of Vector Neural Network Instructions | ||||
| Software Emulation ARM64 | 2017 | Windows 10 on ARM64 | Cooperation between Microsoft and Qualcomm bringing Windows 10 onto ARM64 platform with x86 applications supported by CHPE emulator starting from 1709 (16299.15) | ||||
| Era | Release | CPU models | Physical Address Space | New features | |||
- 1 2 Intel 64 and IA-32 Architectures Optimization Reference Manual (PDF). Intel. Rujan 2019. 3.4.2.2 Optimizing for Macro-fusion
- 1 2 Fog, Agner. The microarchitecture of Intel, AMD and VIA CPUs (PDF). str. 107.
Core2 can do macro-op fusion only in 16-bit and 32-bit mode. Core Nehalem can also do this in 64-bit mode.